Šablon:CPU tehnologije — Википедија

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p r u CPU tehnologije
Architecture	Harvard Modified Harvard von Neumann Dataflow Comparison
Instruction set	ASIP CISC EDGE EPIC MISC OISC RISC VLIW NISC ZISC
Word size	1-bit 4-bit 8-bit 9-bit 10-bit 12-bit 15-bit 16-bit 18-bit 22-bit 24-bit 25-bit 26-bit 27-bit 31-bit 32-bit 33-bit 34-bit 36-bit 39-bit 40-bit 48-bit 50-bit 60-bit 64-bit 128-bit 256-bit 512-bit variable
Pipeline	Instruction pipelining In-order & out-of-order execution Branch predictor Register renaming Speculative execution Hazards Bubble
Parallel level	Bit Bit-serial Word Instruction Scalar Superscalar Data Vector Task Thread
Multithreading	Temporal multithreading Simultaneous multithreading Hyper-threading
Flynn's taxonomy	SISD SIMD MISD MIMD SPMD
Types	Digital signal processor Microcontroller System on a chip Cellular
Components	Arithmetic logic unit Barrel shifter Floating-point unit Back-side bus Multiplexer Demultiplexer Registers Memory management unit Translation lookaside buffer Cache Register file Microcode Control unit Clock rate
Power management	APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating